The present invention relates to the field of integrated circuits and integrated circuit manufacturing. More particularly, the present invention relates to the interconnection of electronic circuit structures and to blocking diffusion of high-conductivity structures using a thin barrier layer that is useable in downwardly scaled semiconductor structures.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) devices, such as p-channel MOS (PMOS), n-channel MOS (NMOS), complimentary MOS (CMOS), BiCMOS devices, and bipolar transistors. Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed and connected to other circuitry using metal interconnects extending from metal layers formed above the devices. The particular structure of a given active device can vary between device types. For example, a MOS transistor generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions. Depending on the circuit design, one or more metal layers are formed above such MOS transistors with lower level metal interconnects extending to various portions of the MOS transistors, such as to the gate electrodes and the source/drain regions.
In the past, the metal interconnects have been typically formed from aluminum alloys. By the late 1 990s, other metals, including copper, have been increasingly used and considered because of their improved conductivity and improved resistance to electromigration.
One important step in the manufacture of such devices is the formation of barrier or isolation regions to prevent diffusion from the metal layers to the active areas of the semiconductor devices. Diffusion occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to a region of the silicon wafer and dopant atoms in the silicon wafer region. Diffusion is problematic in a number of areas including, for example, in copper-based interconnect systems processed using technologies below about 0.25 xcexcm and the xe2x80x9cdual-Damascenexe2x80x9d approach, where vias and metal lines are formed simultaneously into dielectric slots. To prevent copper diffusion into the active area of the device, various barrier metal or metal-compound films have been used including, for example, Ta and TaN at barrier thicknesses of about 300 xc3x85 to 500 xc3x85. Preventing diffusion of copper is important, because the presence of copper in the substrate silicon causes an increase in pn junction leakage and threshold voltage shifts in MOS devices. Such diffusion has also caused reduced dielectric breakdown.
As downward scaling of semiconductor structures continues and processing approaches 0.06 xcexcm (600 xc3x85) levels, for example, conductive barrier films having thicknesses in the range of 300-500 xc3x85 will be prohibitively thick to the practical manufacture of such semiconductor structures. For example, a via having a width of 0.06 xcexcm would be filled completely with a barrier film coating of only 300 xc3x85 in thickness. Further, because the resistivity of many barriers materials is quite high, a significant increase in sheet resistivity (xe2x80x9cRsxe2x80x9d) for copper lines, formed by the Damescene process, would occur with even thinner barriers. The resistivity of TaN, for example, is about 150 times higher than the resistivity of copper.
For such small via structures, in addition to the sidewall barrier thickness being a concern, the barrier material at the base of the opening would cause an increase in via resistance. For example, the resistance across the barrier in a 0.06 xcexcm wide via using a 300 xc3x85 TaN bottom coating would be about 20 ohms.
While the above discussion evidences the need to reduce the barrier thickness for downwardly scaled semiconductor structures, an analysis of prior art suggests that the thickness of certain barrier materials against diffusion of the highly-conductive metals (such as copper and silver) can be reduced to thicknesses to about 100 xc3x85 without adversely impacting circuit operation. A more detailed analysis of published data on bias/temperature studies, on the effect of barrier thickness on dielectric failure (high leakage), suggests that for TaN barriers, a rough estimate for a minimum barrier thickness is on the order of 20 xc3x85. This estimate is based on a number of assumptions that may or may not be applicable for a given application. Among others, these assumptions include: a median time to failure t50 of about 106 hours is needed at an operating temperature of 150xc2x0 C., (consistent with a long term failure percent of 0.1 at 106 hours and a log normal sigma of 0.8), and an acceleration factor to 275xc2x0 C. (estimated on the basis of the activation energy of Cu diffusion in Cr). The temperature of 275xc2x0 C. is the level at which there have been relevant studies of dielectric failure due to copper diffusion, with reported data on the median time to failure (t50) for several thickness of TaN. For further information concerning such work, reference may be made to VMIC Conference Proceedings, June 10-12, 1997. p.87. The test device employed in this work was under an electric field of 2 MV/cm. This data can be plotted as t50 versus the barrier thickness xe2x80x98xxe2x80x99 yielding the relationship:
t50=kx,
where k=0.23 hours/xc3x85.
Using the above target value of t50 and the acceleration factor, a minimum barrier thickness for TaN is estimated to be on the order of 20 xc3x85.
At the less aggressive operating temperature of 125xc2x0 C., according to the present invention, an analysis based on the above reasoning suggests that a barrier on the order of a single monolayer would suffice. Thus, the very thin barrier films suggested in connection with the present invention would range from less than 60 xc3x85 to a monolayer of material depending, of course, on the diffusion coefficient (D) of the barrier.
The above estimate is for a sufficient barrier thickness to protect the dielectrically-insulated interconnects, where electric fields on the order of 2xc3x97105 V/cm might be present. The diffusion rate of copper is greatly accelerated by an electric field, but with a conductive barrier in place, the amount of copper transported into a dielectric is controlled by thermal diffusion rates only. But to protect underlying active devices and pn junctions, additional protection is necessary.
One prior art approach for forming copper-based interconnects or vias is illustrated in FIGS. 1A-1C. Beginning with FIG. 1A, the approach involves a plasma etching process to open a trench 110 through a SiN layer 112 and through an underlying SiO2-based dielectric layer 114. The plasma etching process terminates when the trench 110 reaches a conductive contact region 116 under the SiO2-based dielectric layer 114. As shown in FIG. 1B, a barrier layer 120 of sufficient thickness to protect underlying active transistors is then formed, followed by sputter deposition or electroplating of copper 122. A chemical-mechanical polishing (CMP) process is then used to planarize the structure down to the top of the SiN layer 112. The polished structure is shown in FIG. 1C. The SiN layer 112 acts as a hard polishing stop for the CMP process, and also inhibits copper diffusion into lower levels from the copper source and from any copper interconnects above the one shown in FIG. 1C.
One problem with this approach relates to the SiN layer 112 having a relatively high dielectric constant. The dielectric constant of the SiN layer 112 is about 7.5, whereas the dielectric constant of the SiO2-based dielectric layer 114 is only about 3.9. This differential increases the capacitive coupling between interconnect levels that may be formed on the structure. This increased coupling adversely effects RC delays in the integrated circuit.
Accordingly, there has been a need for semiconductor structures, and manufacturing processes therefor, that are consistent with efforts to downward scale semiconductor structures while overcoming the above-discussed disadvantages.
According to various aspects of the present invention, embodiments thereof are exemplified in the form of manufacturing methods and structures involving diffusion barrier layers (or films) for highly-conductive metals such as copper and silver. One example implementation is directed to a process for fabricating a semiconductor device having an active area below a first level of metal interconnects. The process involves: forming a dielectric barrier against diffusion of a highly conductive metal, wherein the highly conductive metal in pure form is more conductive than aluminum; forming a refractory metal connecting device or plug that penetrates the dielectric barrier and makes electrical contact with a doped semiconductor material; forming a first level interconnect of the highly conductive metal, the highly conductive metal covered on the sides and on the bottom with a conductive barrier film that partially blocks (as compared to completely blocking) diffusion of the highly conductive metal at an operating temperature of the semiconductor device, wherein the dielectric diffusion barrier lies above the active area and lies below but not in direct contact with the first level of metal interconnects and blocks diffusion that is not blocked by the conductive barrier film.
Another example implementation of the present invention is directed to a method for fabricating a semiconductor device. The method includes: forming active devices on a semiconductor substrate and a first insulating film over the active devices; forming a dielectric barrier against penetration of copper over the first insulating film; forming a second insulating film over the dielectric barrier; forming an opening in the first and second insulating films and the dielectric barrier to doped semiconductor regions; filling the opening with a refractory metal; forming a third insulating layer over the refractory metal and the second insulating film; forming an opening to the refractory metal in the third insulating layer; and forming a thin barrier to copper diffusion within the opening; and filling the opening with copper.
Another example implementation of the present invention is directed to a semiconductor device involving a dielectric barrier for blocking diffusion of a highly conductive metal. The structure includes a dielectric barrier against diffusion of a highly conductive metal. The highly conductive metal in pure form is more conductive than aluminum, and the diffusion barrier lies above the active area and below but not in direct contact with the first level of metal interconnects. A refractory metal connecting device penetrates the dielectric barrier and makes electrical contact with a doped semiconductor material located on a side of the dielectric barrier opposite the first level of metal interconnects. The highly conductive metal is covered on the sides and on the bottom with a conductive barrier film, and the conductive barrier film is adapted so that it only partially blocks (as compared to completely blocking) diffusion of the highly conductive metal at an operating temperature of the semiconductor device.
Another embodiment of the present invention is also directed to a semiconductor device, but with the semiconductor device constructed with: a dielectric barrier layer; a thin, conductive, partial-diffusion barrier and adhesion promoting film; and a highly-conductive-metal interconnect patterned over the thin, conductive, partial-diffusion barrier and adhesion promoting film. Further, a thin barrier film is arranged to coat the metal interconnect on its upper surface and edges, and the metal interconnect overlies but is not in direct contact with the dielectric barrier layer. In a more specific embodiment, the highly-conductive-metal interconnect is copper or a copper alloy.
Another embodiment of the present invention is directed to a method for fabricating a semiconductor device having active devices. This method comprises: covering a highly-conductive metal-based connecting means on the edges and lower surface with a conducting barrier and adhesion improvement film, the conducting barrier and adhesion improvement film selected to partially block the high conductivity metal diffusion at the operating temperature of the semiconductor device; and forming on the semiconductor substrate an insulating barrier film to the highly-conductive metal-based connecting means, the insulating barrier film laying between the metal based connecting means and the active devices, wherein the insulating barrier film is not in direct contact with the active devices and the highly-conductive metal-based connecting means.
The above summary is not intended to provide an overview of all aspects of the present invention. Other aspects of the present invention are exemplified and described in connection with the detailed description.